1. Field
Example embodiments are directed to a semiconductor device, and for example, to a semiconductor device capable of changing a pipe line of an on-die termination control circuit for controlling termination resistance, and a method of operating the same.
2. Description of the Related Art
Operating speed, i.e., operating frequency of electronic devices, including semiconductor devices, may be increasing and the swing width of a signal interfaced for low-power operation may be decreasing. However, as the swing width of the signal decreases, influence of external noise may be increasing and there may be a problem in the reflectivity of the signal due to impedance mismatching at an interface terminal.
The impedance mismatching may occur due to variation in a process, variation in a voltage, and/or variation in temperature (PVT variation) as well as external noise. When impedance mismatching occurs, the interface signal may be distorted and transmitting data may become difficult. Bus termination technique may present an opportunity to reduce the distortion of the signal. The termination technique may include mother board termination and on-die termination (ODT). ODT may refer to impedance matching allowing bus termination to be accomplished at an input/output port of a semiconductor device.
Conventional semiconductor devices may include an ODT control circuit generating a termination resistance control signal in response to a first clock signal and a first ODT signal, a termination resistance generator generating termination resistance in response to the termination resistance control signal, and a data transceiver receiving/transmitting data from/to a data line which is impedance-matched to the terminal resistance.
The ODT control circuit may include a clock buffer, a delay-locked loop (DLL), an ODT buffer, and a control block. The clock buffer may buffer the first clock signal and generate a second clock signal. The DLL may generate a third clock signal synchronized with the first clock signal. The ODT buffer may buffer the first ODT signal and generate a second ODT signal. The control block may generate the terminal resistance control signal in response to the second clock signal, the third clock signal, and the second ODT signal.
FIG. 1 is a block diagram of a control block 100 that may be included in a conventional ODT control circuit. Referring to FIG. 1, the control block 100 may include a flip-flop 110, a pipe line circuit 120, a first repeater 130, a second repeater 140, and an ODT gate 150.
The flip-flop 110 may synchronize a second ODT signal BODT with a second clock signal BCLK so as to output a third ODT signal SODT. The pipe line circuit 120 may synchronize the third ODT signal SODT with a third clock signal DLL_CLK so as to output a fourth ODT signal SODT2.
The first repeater 130 may improve the current driving ability of the fourth ODT signal SODT2 so as to generate a fifth ODT signal D_SODT2. The second repeater 140 may improve the current driving ability of the third clock signal DLL_CLK so as to generate a fourth clock signal D_DLL_CLK. The ODT gate 150 may synchronize the fifth ODT signal D_SODT2 with the fourth clock signal D_DLL_CLK so as to generate a termination resistance control signal CSTR.
Since conventional semiconductor devices may receive an ODT signal using an ODT buffer, it may be difficult to secure a time margin in the semiconductor devices when higher-speed operation is required. For example, a termination resistance control signal may lag or lead a latency specification of a semiconductor device according to an operating frequency of the semiconductor device. Latency indicates a time period between when a semiconductor device receives a command from a controller and when the semiconductor device outputs a control signal for executing the command, which may be expressed with respect to a cycle of a clock signal.
As the operating frequency of a semiconductor device may be increasing and a path for transmitting a clock signal and a path for transmitting an ODT signal may have different latencies due to PVT variation, it may become more difficult to transmit a command with time margin secured with respect to a wider frequency range.